1. Field of the Invention
The invention relates in general to ultra scale integrated circuits, and more particularly to a method of fabricating copper interconnects in ultra scale integrated circuits.
2. Description of the Related Art
The fabrication of deep submicron ultra large scale integrated (ULSI) circuits requires long interconnects having small contacts and small cross-sections. To achieve the above objectives, the preferred interconnect material is copper. Copper provides a number of advantages for wiring applications including low resistivity and a high melting point.
At present, aluminum is the material used in fabricating interconnects on most integrated circuits. This invention seeks to replace the aluminum with copper in the fabrication of advanced circuits and ultra-fast logic devices.
Many problems, however, are encountered in fabricating circuit interconnects with copper. Some of the major difficulties include: (a) copper oxidizes easily at low temperatures; (2) copper has poor adhesion to substrates; (3) copper diffuses into silicon dioxide and other dielectric material used in micro-circuitry; and (4) copper requires a high temperature for patterning by reactive ion etching.
In order to overcome these disadvantages when using copper as an interconnect material, it is necessary to passify the copper surfaces and provide diffusion barriers between the copper and the adjacent layers. A layer of titanium nitride (TiN) has been suggested as a possible diffusion barrier due to its inert and conductive nature.
FIGS. 1A-1D are cross-sectional views showing a conventional method of fabricating copper interconnects. Referring to FIG. 1A, a semiconductor substrate 100 is provided. A dielectric layer 104 with a via 102 is formed on the semiconductor substrate 100. A titanium layer 106 is formed, for example, by sputtering in the via 102 and on the dielectric layer 104 under argon gas. The titanium layer 106 has a thickness of about 200-500 .ANG..
Referring to FIG. 1B, a first titanium nitride layer 108 is formed, for example, by nitriding under N.sub.2 gas or NH.sub.3 gas at high temperature on the titanium layer 106 as a adhesion layer.
Referring to FIG. 1C, a copper layer 110 is formed on the first titanium nitride layer 108. Excess copper material outside of the via 102 is removed by chemical mechanical polishing to expose the semiconductor substrate 100.
Referring to FIG. 1D, a second titanium nitride layer 112 is formed on the copper layer 110 to avoid the oxidation and preserve the characters of the interconnections. The process of fabricating copper interconnects described above provides a copper layer in the via as an interconnect. A titanium layer and a titanium nitride layer are deposited between the copper layer and other dielectric layers as a barrier layer and an adhesion layer to protect the copper layer from oxidation and prevent it form diffusing.
A number of limitation to the above method have been discovered, however, particularly when forming fully-planar copper lines by filling grooves in a dielectric and removing the excess. In this case, the copper must be deposited into a feature without leaving a void, so electroplating or chemical vapor deposition is required. It is difficult to deposit refractory copper or metal-copper alloys, such as copper-titanium, with electroplating or chemical vapor deposition techniques.